ATE Test Engineer , Amazon Leo

Amazon Leo is an initiative to launch a constellation of Low Earth Orbit satellites that will provide low-latency, high-speed broadband connectivity to unserved and underserved communities around the world.

Come work at Amazon!

As an ATE Test Engineer, you will engage with an experienced cross-disciplinary staff to conceive, design, and develop innovative test solutions for products developed for and deployed in Amazon Leo phased array antennas in LEO satellites and ground terminal products. You'll be a key contributor to defining and developing characterization and validation ATE test methodology for Amazon Leo custom silicon, helping take devices from silicon bring-up through release to high-volume production. You will contribute across digital, high-speed I/O, and RF test, and support the design and verification of the ATE hardware that enables it. You must be responsive, flexible, and able to succeed within an open, collaborative peer environment.

Export Control Requirement
Due to applicable export control laws and regulations, candidates must be a U.S. citizen or national, U.S. permanent resident (i.e., current Green Card holder), or lawfully admitted into the U.S. as a refugee or granted asylum.


Key job responsibilities
• Design, review, and verify ATE hardware (load board, socket, and probe card) for signal and power integrity, with attention to high-speed and RF interfaces, collaborating with external vendors through the hardware design and build process.
• Implement and optimize test programs for mm-wave System-on-Chips (SoCs) on ATE platforms such as Teradyne/Advantest and ensure seamless integration into high-volume manufacturing environments.
• Implement and optimize RF, mixed-signal, and high-speed interface test routines for high-volume manufacturing.
• Implement on-chip calibration techniques for analog and mixed-signal circuits and validation of calibration accuracy across process/voltage/temperature (PVT) corners.
• Partner directly with DFT teams to define test insertion strategy, review pattern quality, resolve coverage gaps, and optimize scan/MBIST/BIST content for ATE execution.
• Drive test program release to production, ensuring test readiness, quality, and yield targets are met at hand-off to high-volume manufacturing.
• Optimize test time, yield, and repeatability across process, voltage, and temperature.
• Support RMA and field-return debug, using test and characterization data to root-cause and resolve downstream quality issues